Non-volatile latch cells are known in the art and can be used in various programmable circuits, for example, to program logic circuits or I/O circuits into different modes, or to store trim settings for analog circuits, among many other uses.
Some non-volatile latch circuits can include numerous transistors with a corresponding large layout area (˜100 μm2), and require complicated signals to power-up correctly.
A SONOS non-volatile latch 100 is shown in FIG. 1. Latch 100 uses a trigate structure including one SONOS transistor (the non-volatile element) and two MOS transistors (used to isolate the SONOS transistor for programming and erasing modes) known as the STR (Store) transistor and the RCL (Recall) transistor. The SONOS transistor is a type of charge trapping transistor where charge stored in a nitride layer makes a non-volatile memory device/transistor.
In a lower portion of the circuit, latch 100 uses a first SONOS device including MOS transistors T5 and T3, and SONOS transistor T1, and a second SONOS device including MOS transistors T6 and T4, and SONOS transistor T2. The Vneg and Vspw voltages shown next to various transistors in FIG. 1 are substrate voltages of the transistors. The gates of transistors T5 and T6 are coupled together to receive the LOAD signal, the gate of transistor T1 receives the TEST_P signal, the gate of transistor T2 receives the TEST_N signal, and the gates of transistors T3 and T4 receives the PROGRAM_L signal. The sources of transistors T3 and T4 are to receive the Vspw voltage. In latch 100, transistor T1 is erased, and transistor T2 is programmed. The lower portion of latch 100 is coupled to an upper circuit portion including P-channel transistors T11, T12, T13, and T14, as well as N-channel transistors T7, T8, T9, and T10. Vltch is the substrate voltage of the PMOS devices T11, T12, T13, and T14. The sources of transistors T11, T12, T13, and T14 receive the Vpwr voltage. The gates of transistors T13 and T14 receive the EQUALIZE signal, the gate of transistor T11 is coupled to the drain of transistor T13, the gate of transistor T12 is coupled to the drain of transistor T14, the gates of transistors T9 and T10 receive the HOLD signal, the gate of transistor T7 is coupled to the drain of transistor T13, and the gate of transistor T8 is coupled to the drain of transistor T14. The sources of transistor T7 and T8 receive the Vneg voltage. Node ID is coupled to capacitor CID, and NODE IDM is coupled to capacitor CIDM. These capacitors are parasitic capacitors and input capacitors of the other circuits connected to the latch.
Latch 100 uses fourteen transistors, consumes a great deal of integrated circuit area, and relies on complicated signals. The EQUALIZE_L, LOAD, HOLD, SB, and SA signals are shown in the corresponding timing diagram of FIG. 2, as well as the equalize, delay, and latch modes of operation. Latch 100 also has a possible undesirable mode of operation. If node voltages ID and IDM have not turned on transistors T11 and T12 before the hold signal turns on, then the mismatch of the threshold voltages of transistors T9 and T10, instead of the programming and erasing of transistors T1 and T2, will determine the logic state of latch 100.